Constant-complexity, deterministic, very fast memory allocator (heap) for hard real-time high-integrity embedded systems. Allocation takes ≈120 cycles @ RP2350 irrespective of heap usage. There is little activity because the project is finished and does not require further changes.

Event-driven, preemptive, priority-based, hardware RTOS for ARM Cortex-M.

Real-time Actor-based Message Exchange Network 🍜

SuperTinyKernel RTOS is a lightweight, high-performance, deterministic, bare-metal C++ RTOS for resource-constrained embedded systems based on ARM Cortex-M and RISC-V MCUs. Includes with x86 emulator. Suits systems with limited RAM/FLASH.

Simulation Framework for the Static Scheduler

Stoic-V: a deterministic RV32IM + Zba/Zbb/Zbs + Zicsr (M-mode) RISC-V soft core in SystemVerilog. No caches, speculation, or branch prediction, so timing is operand-independent and WCET is statically analysable. Drop-in replacement for the AMD MicroBlaze-V via the LMB v10 interface; closes 250 MHz on UltraScale+.

custom riscv embedded profile, replacing volume II (aka riscv privileged)

A C and C++ library package suitable for real time development

Real Time Systems Course. Project 1: Cyclic Scheduling

Real Time Systems Course. Project 2: Priority Scheduling

Deterministic Real-Time Memory Allocator