This repository documents the Design for Test (DFT) Flow that I am currently exploring during my internship.
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Jul 31, 2025 - Stata
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rtl-synthesis
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These are verilog codes that are synthesized using open source tool yosys. We can do technology mapping using netlist, we can also estimate the area of design using info given in library.
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Dec 4, 2024
4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground
mapping system-verilog yosys digital-design vlsi-design open-source-eda rtl-synthesis abc-tech eda-playground 4bit-alu
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Jun 5, 2026 - SystemVerilog
8-bit CPU RTL synthesis flow using Verilog, Yosys, SKY130 standard cells, OpenSTA timing analysis, and ASIC-readiness documentation.
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Jun 26, 2026 - Verilog
This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.
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Apr 11, 2021
A parameterized multi-cycle Harvard architecture processor designed from the ground up in Verilog. Developed using a complete RTL design workflow including simulation, linting, synthesis, Sky130 technology mapping, area estimation, static timing analysis, cocotb self-checking testbenches and post synthesis GLS 🖥️.
verilog computer-architecture instruction-set-architecture microarchitecture computer-organization performance-modeling turing-complete static-timing-analysis harvard-architecture computer-design rtl-synthesis amdahls-law self-checking-testbenches
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Jul 21, 2026 - Verilog
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